0.18 微米設計單元資料庫

透過提供眾多廠商的綜合免費設計單元資料庫，聯電重新改革了晶圓專工產業。 除此之外，聯電同時還提供其他的收費設計單元資料庫。

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免費設計單元資料庫

Artisan 0.18um Library

Standard Cell 478 high-density standard cells 9-track cell architecture Average cell density of 111K gates/sq.mm Multiple drive strengths Routable in 3, 4, 5 or more metal layers Comprehensive design tool support Process specific electrical and physical tuning   Single-Port Synchronous SRAM Generators Optimized for high density and high speed Flex-RepairTM redundancy implementation option   - Includes separate Fuse-Box Generator   - Supports flexible BIST implementation Broadly configurable to up to 512k bits:   - 256 to 16k words deep (word increment = 2 x column mux)   - 2 to 128 bits wide (bit increment = 1) User-configurable mask write option (1 to 36 bit segments) Aspect ratio control for efficient floor planning (column mux options: 4, 8, 16) Memory operation and data retention at low voltage and down to 0 MHz Low active power and leakage-only standby current Accurate timing and power models Complete set of models supporting industry-leading design tools Robust design practices and validation procedures ensure successful designs Extensive silicon validation

Dual-Port Synchronous SRAM Generator Optimized for high density and high speed Two fully-independent read/write ports Broadly configurable to up to 256k bits:   - 128 to 8k words deep (word increment = 2 x column mux)   - 2 to 128 bits wide (bit increment = 1) User-configurable mask write option (1 to 36 bit segments) Aspect ratio control for efficient floor planning (column mux options: 4, 8, 16) Memory operation and data retention at low voltage and down to 0 MHz Low active power and leakage-only standby current Accurate timing and power models Complete set of models supporting industry-leading design tools Robust design practices and validation procedures ensure successful designs Extensive silicon validation     Inline I/O 600+ 3.3V/5VT Pad pitch: 60 um Input: pull-up/pull-down,Schmitt trigger,LVTTL,CMOS Output: multiple current up tp 24mA with 3 slew rate options Special pads: clock, crystal oscillator, corner, power and ground

Virtual Silicon 0.18um Library

Standard Cell 500+ high performance standard cells 11-track cell architecture, performance optimized for 200~700 MHz Average cell density of 90K gates/sq.mm Multiple drive strengths Layout using metal 1 only Scan version of every flip-flop available Fully contacted well ties Accurate modeling and characterization for timing and power Open architecture developers kit available     Inline and Staggered I/O 700+ 3.3V & 3.3V/5VT I/O pads Pad pitch: 60um (In-line), 40um (Staggered) Multiple current drives up to 24mA Input: Pull-up/pull-down resistor, pad keeper, normal/ Schmitt Output and bi-directional with slew rate control Silicon proven ESD and latch-up structures Analog power pads, crystal pads Open architecture developers kit available

Single Port Synchronons SRAM Synchronous reads/writes Static design with zero standby current Byte write capability Routable over the core with higher metal layer Ability to compile to multiple aspect ratio Scan and BIST support

Faraday 0.18um GII Library

Standard Cell 400+ high performance standard cells 9-track cell architecture Average cell density >120K gates/sq.mm Optimized multiple drive strengths High porosity and routability Scan version of every flip-flop available Ultra low power cell available Gated input for preventing leakage Fully tool models support

Analog Excellent high PSRR and low jitter Phase-Locked Loops   Single Port SRAM, Dual Port SRAM, One Port Register File, Two Port Register File, and Via2 ROM Compilers Synchronous reads/writes Static design with zero standby current Byte write capability Provides both high speed and low power SRAMs Ability to compile to multiple aspect ratio Scan and BIST support Power port connections support Zero hold time for inputs

Inline and Staggered I/O
1.8V, 3.3V I/O pads 1.8V/2.5VT, 3.3V/5VT I/O pads Support over 500+ IO Functions Pad pitch: 65um (In-line), 40um (Stagger)	Programmable current drives and slew rate control from 2mA to 16mA Programmable pull-up/pull-down resistor, normal/ Schmitt trigger Provide 90+ programming features in one I/O In-line to staggered I/O corner available

Faraday 0.18um LL Library
Standard Cell 400+ high performance standard cells 9-track cell architecture Average cell density >120K gates/sq.mm Optimized multiple drive strengths High porosity and routability Scan version of every flip-flop available Ultra low power cell available Gated input for preventing leakage Fully tool models support	Analog Excellent high PSRR and low jitter Phase-Locked Loops     Single Port SRAM, Dual Port SRAM, Two Port Register File and Via1 ROM Compilers Synchronous reads/writes Static design with zero standby current Byte write capability Provides both high speed and low power SRAMs Ability to compile to multiple aspect ratio Scan and BIST support Zero hold time for inputs

Inline and Staggered I/O
1.8V, 3.3V I/O pads 1.8V/2.5VT, 3.3V/5VT I/O pads Support over 500+ IO Functions Pad pitch: 65um (In-line), 40um (Stagger)	Programmable current drives and slew rate control from 2mA to 16mA Programmable pull-up/pull-down resistor, normal/ Schmitt trigger Provide 90+ programming features in one I/O In-line to staggered I/O corner available

Dolphin Technology 0.18um Library
Standard I/O		Special Purpose I/Os
	Staggered pad design with 35,50,70 um pitch		LVDS, LVTTL, LVPECL, HSTL Class I/II (DDR)
	I/O pads for flip chip(C4) 240um &250um		PCI-X for 133 MHz operation and PCI-66/33 MHz
	I/O Drive strengths 2/4/6/8/10/12mA 1.8V core with 3.3V output		PVT (Process, Voltage and Temperature) compen sated drive strength buffer
	Pull-up, pull-down, sustain level options		HyperTransportTM (LDT) RX/TX Macro @1.6Gb/s
	4 different slew rate keeper options, JTAG inputs for testability, Schmitt trigger inputs
	Level shifts from 1.8 V core up to 3.3 V I/O supply

Artisan 0.18um Library
Standard Cell		In-line and staggered I/O
	1000+ High Performance standard cells		3.3V/5VT
	9-track cell architecture		Pad pitch: 76.8um (In-line), 38.4um (Staggered)
	Average cell density of 73K gates/sq.mm		Multiple current drives up to 16mA
	Multiple drive strengths		Pull ups, Pull downs, switchable
	Silicon proven		Hysteresis
	Scan version of every flip-flop available		Built-in level shifting
	Compatible with mixed signal environment
	Accurate timing and power models

Faraday 0.18um GII Library
Analog
	10-Bit DAC 200MHz
	8-Bit ADC 135MHz
	Power-on-reset circuit
	Low VDD Detector
	RC oscillators
	Voltage Regulators
	Comparators
	Crystal pads

Faraday 0.18um LL Library

Analog 10-Bit DAC 200MHz 8-Bit ADC 135MHz Power-on-reset circuit Low VDD Detector RC oscillators Voltage Regulators Comparators Crystal pads