System
Architecture Knowledge
    IP and Design Methodology
    Process Technologies
    R&D
    65 nm
    90 nm
    0.13 um
    0.15 um
    0.18 um
    0.25 um and above
    Mixed Mode/
RFCMOS
    CMOS Image
Sensor
    High Voltage
    World Class Manufacturing
    Test and Package Solutions
    Design Support Manuals

 

0.15um


We are currently in mass production for our high performance 0.15um process, which is targeted for multiple applications including computing, wired, and wireless communications. UMC's available IP/Libraries for the 0.15um process allow more than 150k logic gates/mm, and feature the industry's richest set of I/O pads and unique PLL compilers.

Technology Key Features

  • Shallow trench isolation
  • P-sub, Twin-Well (Epi-wafer option)
  • Dual gate oxides
  • Dual poly gate with CoSi2
  • CoSi2 S/D
  • Up to 1P7M Al (top 2 layer Cu option)
  • 3.15 SRAM bit cell
  • Wirebond / Flipchip packaging



0.15um Devices Offering